Verilog is a Hardware Description Language; a textual format for describing electroniccircuits and systems. Applied to electronic design, Verilog is intended to be usedfor verification through simulation, for timing analysis, for test analysis (testabilityanalysis and fault grading) and for logic synthesis.

The Verilog HDL is an IEEE standard - number 1364. The first version of the IEEEstandard for Verilog was published in 1995. A revised version was published in 2001;this is the version used by most Verilog users. The IEEE Verilog standard documentis known as the Language Reference Manual, or LRM. This is the complete authoritativedefinition of the Verilog HDL.

A further revision of the Verilog standard was published in 2005, though it haslittle extra compared to the 2001 standard. System Verilog is a huge set of extensionsto Verilog, and was first published as an IEEE standard in 2005. See the appropriateKnowhow section for more details about System Verilog.

IEEE Std 1364 also defines the Programming Language Interface, or PLI. This is acollection of software routines which permit a bidirectional interface between Verilogand other languages (usually C).

Note that VHDL is not an abbreviation for Verilog HDL - Verilog and VHDL are twodifferent HDLs. They have more similarities than differences, however.

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