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Verilog Training Syllabus

  • INTRODUCTION
    • Introduction to top down digital designflow
    • Levels of abstraction – Structural, RTL,Behavioral
    • Introduction to Verilog HDL
    • Modeling at various abstraction levels
  • VERILOG BASICS
    • Anatomy of a Verilog Model
    • Data types
    • Logic Values
    • Identifiers
    • Numbers
    • Parameters
    • Procedural Blocks: Initial and Always
    • Continuous Assignments
    • Operators
    • Conditional Statements
    • Loop Statements
  • BEHAVIORAL VERILOG
    • Procedural Constructs
    • Timing Control
    • Block Statements
    • begin - end,fork - join
    • Procedural Continuous Assignments
    • assign - deassign,force – release
  • Modeling Techniques
    • Combinatorial Logic
    • Sequential Logic
    • Gate Level Modeling
    • Switch Level Modeling
  • MISCELLANEOUS
    • Compiler Directives
    • System Task and Functions
    • Array of instances
    • File IO
    • Memory modeling, array access
  • SYNTHESIS PERSPECTIVE
    • Synthesis flow in brief
    • Guidelines for Combinatorial block
    • Guidelines for Sequential block
    • Blocking & Non-blocking assignments
    • FF, latch inference
    • FSM Modeling
  • VERIFICATION PERSPECTIVE
    • Verification Flow
    • Introduction to Testbench
    • Writing Test Bench
    • Sample Test Bench
  • GATE LEVEL MODELING
    • Verilog Primitives
    • User Defined Primitives
    • Modeling Delays
  • TIMING SPECIFICATION CAPTURE
    • Specify Block
    • Setup and Hold Time
  • VERILOG PLI
    • Introduction to PLI
    • PLI Capabilities
    • Steps to Integrate PLI
  • VERILOG 2001 ENHANCEMENTS
  • SUBROUTINES IN VERILOG
    • Task
    • Function
    • Subroutine types – Static and Automatic
  • ADVANCED VERILOG
    • Compiler Diectives:define,undef,resetall,ifdef,ifndef
    • Parameter
    • Generate
    • Timescale
    • Display Tasks-display $monitor
    • Value Change Dump
    • Formattime, Timeformat, Printtimescale
    • Understanding Blocking and Non-blockingAssignments
  • PROJECT DESCRIPTION
  • PROJECT IMPLEMENTAION
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